`timescale 1ns / 1ps

module writeReadSRAM(Clock_i, writeEnable_i, dataWrite_i, dataRead_o, dataSRAM_io);

	input Clock_i,
		   writeEnable_i;
			
	input [7:0] dataWrite_i;
	output [7:0] dataRead_o;
	inout [7:0]	dataSRAM_io;
	wire wireEnable, wireWrite, wireRead;
	
	nor OR(wireEnable, !Clock_i, writeEnable_i);
	
	flipFlopD dWrite(.input_i(dataWrite_i),
	                 .Clock_i(Clock_i),
						  .output_o(wireWrite));
						  
	flipFlopD dRead(.input_i(dataSRAM_io),
	                 .Clock_i(Clock_i),
						  .output_o(dataRead_o));
						  
	triStateDriver triState(.input_i(wireWrite), 
				               .output_o(dataSRAM_io),
									.enable_i(wireEnable));
									
	

endmodule
